1. Field of the Invention
The present invention relates generally to integrated circuits and more specifically, the present invention relates to the testing of integrated circuits.
2. Description of the Related Art
Present state of the art methods for detecting open circuit defects in CMOS integrated circuits include Boolean logic and IDDQ tests. FIG. 1 shows a schematic of a simple CMOS integrated circuit 101 with an open circuit defect 107. Integrated circuit 101 includes an inverter 103 with an output coupled to be received by the input of inverter 105. With open circuit defect 107, however, the gates of inverter 105 are decoupled from the output drive of inverter 103 and therefore float at an unknown potential. Moreover, with open circuit defect 107, the level generated at OUT 113 is independent of the level input at IN 111.
With Boolean testing, circuit testers can detect open circuit defects by applying signals of a known level at IN 111 and verify the signals generated at OUT 113. If the signal output at OUT 113 is inconsistent with the signal input at IN 111, open circuit defect 107 may be identified. A limitation with Boolean testing is associated with the fact that modem very large scale integrated circuits commonly have over 10 million transistors. With such a large number of transistors and a limited number of pins, it is very difficult to realize observability of all nodes on the chip. As a result, it is practically impossible to toggle all of the nodes in the chip and thus difficult to screen for open circuit defects within modem CMOS integrated circuits using only Boolean testing.
Another method used to detect defects in CMOS integrated circuits is IDDQ testing. CMOS integrated circuits are popular for their low power characteristics. If the design is static, the current should be nearly zero in an ideal CMOS circuit during standby or a quiescent state. Thus, when a CMOS circuit is not switching states, only a small amount of current should be drawn by the circuit. This quiescent current, commonly referred to as IDDQ, is composed primarily of leakage current. A faulty CMOS circuit may draw a significantly larger amount of current than a properly functioning CMOS circuit when in the quiescent state.
An abnormally high IDDQ may result from a variety of problems which includes defects such as gate oxide shorts, interconnect bridging shorts and interconnect open circuits. By measuring the IDDQ of a CMOS circuit and comparing it with the IDDQ of a known properly functioning CMOS circuit, a faulty circuit can be detected.
In FIG. 1, IDDQ 109 is shown flowing through inverter 105. If the voltage at the gates of the transistors in inverter 105 is high, then the n-channel transistor of inverter 105 is switched off and IDDQ is substantially zero. Conversely, if the voltage at the gates of the transistors in inverter 105 is low, then the p-channel transistor of inverter 105 is switched off and IDDQ 109 is also substantially zero. If, however, there is for example a short circuit defect in a transistor or if the voltage at the gates of the transistors of inverter 105 is at an intermediate value, then both the p-channel transistor and the n-channel transistor will leak a significant amount of current which would therefore result in a substantially high IDDQ 109 current. The abnormally high IDDQ 109 would indicate the presence of a defect.
As shown in FIG. 1, open circuit defects decouple the gates of an input stage from the previous drive stages. Such gates are said to be floating. Since there is no significant conductive path to the gates, the gate potential remains at an unknown value determined in part by minor sources of leakage or by charge placed on the gate during processing. Often, such leakage or processing will set a potential on the gate in which the MOS device is fully shut off. In such a state, which cannot be altered by exercising the part or by any other means open to the test environment, leakage is virtually zero and differentiating such a part from a non-defective part is not possible within a conventional IDDQ test method. For example, in FIG. 1, if the gates of inverter 105 are floating at a logical "0" or "1," IDDQ testing will not detect the open circuit defect 107 since IDDQ 109 will be substantially zero.
Therefore, what is desired is a simple method for detecting open circuit defects in CMOS integrated circuits. Such a method would allow circuit testers to set the voltage at floating gates of an integrated circuit to intermediate values so as to provide better screening for open circuit defects within CMOS integrated circuits.